الفهرس 
AbstractOnly 14 pages are availabe for public view
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Abstract
Great advances in biomedical imaging over the last few decades toward using less intrusive and higher sensitive imaging techniques have made patient diagnosis possible to identify diseases in their early stages. A method of molecular imaging called Positron emission tomography (PET) can produce physiological images processes occurring inside the body. Because of this, PET imaging has a significant advantage in identifying diseases in the very initial stages. More sensitivity and also chemical specificity are provided by PET imaging. One of the PET’s derivatives, called Time of Flight (ToF) imaging, enhances imaging by precisely pinpointing the location of the annihilation event with less than 100 ps of resolution using a Time Digital Converter (TDC). In this case, the readout of the detectors can be done using a Time Digital Converter (TDC), which will provide the photon arrival time. Thus, it improves the PET scanner’s resolution. In order to meet some PET imaging specifications, the proposed TDC provides high resolution and single-cycle latency for high-data-rate applications.
This thesis introduces a multi-stage high resolution time to digital converter TDC architecture based on a Vernier delay line for a PET imaging application. By using multiple stages, the proposed architecture enhances the traditional Vernier delay line by reducing the number of flip-flops and delay components. As a result, speed is increased and power consumption is decreased.
To achieve high resolution using multiple stages, an 8-bit four-stage 0.5Gb/s TDC has been designed and simulated in 130nm CMOS by using Cadence tools. The architecture designed in this thesis is based on a four-stage Vernier delay-line. A 62.5MHz has been used as an input clock signal. The resolutions of the TDC stages are 2ns, 500ps, 125ps, and 31.25ps. The required data signals will be generated by a pulse position modulator PPM circuit with a time resolution of 31.25ps. The simulation results are presented, as well as a comparison of the proposed architecture to other architectures. The proposed architecture circuit consumes 1.277mW of power. And also, the simulation results of the impact of Process, Voltage supply, and Temperature PVT variation are studied on the different four delay lines, which are utilized in both the PPM as well as TDC design.