الفهرس 
Scaling Variation
System Simulation, Layout And Chip Level Veri cationOnly 14 pages are availabe for public view
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Abstract
VLSI circuits continue to explore new areas of contribution in different applications. The CMOS scaling helps in enhancing the spread of VLSI circuits. One of these applications is low-voltage circuits. Low voltage circuits use very low supply voltage to decrease both active and leakage energy. Memories systems, especially SRAMs which spread widely in different applications, will benefit a lot from low-voltage operation.
Consequently, low-voltage operation SRAM memories are attractive. Moreover, they open a new area of contribution. The area of energy constrained applications, which has a lower performance requirements but aggressive energy requirements. So, SRAM that offers read and write functionality at the lowest possible supply voltage will give a great opportunities in this application domain.
This work explores the design of SRAM system blocks able to work within temperature range −40 to 125. Process corners and Monte Carlo analysis are used for further verifi- cation of these blocks and their margins. Furthermore, the limit of low-voltage operation for traditional SRAM and periphery circuits. Moreover, additional circuits as Read and Write assist techniques circuits are implemented to reach a low voltage operation with a normal 6T bitcell. The applied technique gives a great saving in energy compared to other conventional techniques. Also, a timing technique used to overcome assist associ- ated halfselect problem. A test macro of 8-Kbit is designed in 65nm CMOS technology. Simulations show that the design is capable of working down to 0.5V with access time
of 1.77ns in nominal condition and 339ns in low-voltage conditions. The macro is tested on different process corners at both voltage conditions.
In addition to macro design, level shifters for interfacing with memory are also imple- mented with a new technique extending the conversion range of nominal level shifters by
200mV across the same temperature range. Lastly a test chip is implemented for testing purposes with area of 4mm2 packing a memory of 0.9Mbits. Different implementations of the 8-kbit macro are packed helping a fully characterization and testing.