الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
This chapter is concerned with the general aspects of the studies results described in this thesis, as in each chapter the associated concluding, comments have been presented. The following represents a summary of what can be concluded. All the circuits in section (3.3) to (3.4) have some challenges make it’s technique is not suitable for ANN. The differential pair multipliers use resistors as a passive load, and Op-Amp which are consuming in VLSI layouts, and hence cause the area of the multipliers become large. The proper eperation of these circuits requires that the user be aware of the biasing conditions, so that the input voltage V1N is adjusted with the linear range of operation. If the input voltage exceeds than limits, one of Q 1, Q2 will be off and the circuit become unstable, and the dynamic range is low. The THD is usually taken as a measure of the degree of nonlinearity. In the active region, and for the same current swing, the BJT is more linear than the MOS differential pair inputs multipliers. This is to expected due to the second order effect in the relation between the drain current (I D )and gate to source voltage (Vos). So, the attitude towards
using MOS multipliers with active load resistor and no op-amp is more popular and acceptable for ANN. The square low characteristic techniques as shown in section (3.3.3) improves the stability of differential pair inputs, but it’s high THO makes the technique are unsuitable for ANN. Improving stability problems requiring use techniques with a high distortion. Improving the THO requiring the addition of preprocesses circuits which increasing the size. In the last two circuits, presented in sections (3.4), (3.5) these problems are disappeared because there combinations of small area and low THO. The charge based circuit principles such as seen in section (3.5) can produced efficient computation in the analog domain with reduce power and area requirements over classical analog techniques and Massingill analysis shows that the output response of this circuit is linear under special assumption such as neglecting channel length modulation, and mobility reduction .. So, these properties make these multipliers are suitable for use in ANN. The neglecting of channel length
modulation and mobility reduction proved to be significant. Our work shows that accurate analysis of this circuit proves that the actual response of the circuit is not linear also, pseudolinear resistor realization is YDS, Vl’Il dependent. According to the \)re”ious \)rinci\)\e we su~~e”,\. a n.ew c\.~”\l\.\”” n.~\ ~’\.\.\’\ \.\.’\\.~~\.·u~.~ ~~ ~~~ ~\..” ~~’- ~~
””~~”l~’!o ~~ ·’\.~~\le~”e..” l;)\ uni\n source vo1tage and bulk voltage on AC circuit resistance, with taken into consideration these assumptions neglected before. Comparing between our new cJ.rCyj/ and Mundre&.lWa.5S/ng/7/. /nreau.z....ng/ueAC
resistor we find the double MOS differential resistor is superior in linearity. The new suggested circuit is super in linearity compared to Massingill circuit. However, the use of double differential MOS resistor enable it to operate under Vos, V HI variations. The use of buried channel MOS model transistors in the new design makes it un sensitive to mobility reduction effects specially in the case of use a small aspect ratio
( our case ) in contrast Massingill circuit. Since the new circuit operate in the ohmic region, it unsensitive to channel length modulation effects. The dimensions of the transistors in the new circuit can be chosen to be small compared to Massingill circuit. For the same bias voltage and weight inputs, the transient voltage accumulate on the summing bus is lower in the new circuit. Thus, the average actual power consumption over the new circuit will be less than consumed in Massingill circuit. On the other hand, small accumulated charge in the new circuit makes the neuron cell require along time to learn. Our work introduced several modification to this circuit to improve the linearity, die area, and power consumption of circuit. It’s major advantages over other four -quadrant multipliers is its combinations of small area and low power consumption. where, the power consumption can reduced by reducing the aspect ratio of the transistors, without affecting on the major characteristic of the circuit. In addition unlike almost all other designs of four quadrant multipliers, these designs have single ended inputs so that the inputs do not need to preprocessed before
being fed to the multiplier, thus saving additional area. These properties make this tp
multipliers very suitable for ANN.
**There are two major elTects causing deviations from ideal circuits behavior. Mobility reduction 8. As it is process dependent. it can not be made small by optimizing the geomentries of the device. To overcomes from this problem. we recommend by use buried channel MOS model in neural circuit design. Secondarily. Channel length modulation /.... The elTect of channel length modulation can be reduced by using long channel device (The coefficient I, quite smnll for long device. but increases considerably for very short transistor deyicc (our case). but this solution is not acceptnble in our case, because we operating at a vcry large scale and small silicon area is one major aims we want to realize in ANN. In order to ovcrcomcs this problem. we trend to usc our transistor modcl to operating at a triode rcgion. And since /... VDS is so small in ohmic region and hns a lillie cffect on {D.