الفهرس 
AbstractOnly 14 pages are availabe for public view
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Abstract
The increasing gap between processor speed and main memory access time is considered one of the most challenging problems in nowadays computer system design for either uniprocessor or multiprocessor systems. This is because the rate of processor speed technology is much more than memory fabrication technology. There are many researches proposed different techniques to reduce this increasing gap. Buffering, pipelining, outoforder execution, prefetching and caches are examples of these different techniques. Recent researches focusing on cache memory as it is the most promising effective solution. There are two different techniques used to raise hit ratio of cache memory: Software and Hardware techniques. Most of software techniques depends on adding profiling information on running code, which can be used by exploiting the prefetch unit to predict if some code is likely to hit or miss in cache memory or TLB. Hardware techniques propose new hardware logic or suggest the best hardware configuration options according to detailed study to enhance the overall memory system performance. Although these techniques achieve obvious performance enhancement, they are still insufficient. In addition the cache memory it self has many disadvantages: first, it has high power consumption, which make it undesirable in many power constrained applications such as laptops. Second, it occupies large area in IC, which complicate the fabrication process. Third, it is fabricated from static RAM, so it cost much high compared with other types of memories. Last, if it is used as a mapping cache (TLB), it can not generally contain hole mapping table(s) due to its small size. In this research a new enhanced mapping technique is proposed. It is called ?Enhanced Memory Mapping System? EMMS. This technique can be used with or without TLB cache memory. Although TLB is omitted (if we choose this), the performance will increase. This proposed EMMS system is applicable for either uniprocessor or multiprocessor systems. The experiments are performed on a simulator model for paging system to evaluate EMMS performance. The results showed that the proposed EMMS without TLB, enhances the mapping process by 15.21 % compared with standard system with TLB which has hit ratio 90 % and access time faster 10 time more than physical memory access time. But if EMMS performance is compared with standard system without TLB the enhancement will be very near of 100 %. The idea of this technique is that: By exploiting the nature of combinational logic circuit (which has no effective delay) the physical memory can be accessed directly without any mapping process in most code and data. Using this technique most of mapping process part of memory accesses for code and data will be omitted.