الفهرس 
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Abstract
Major bottlenecks are imposed due to the explosion of data transfers and emerging data- intensive applications in heterogeneous system architectures. The conventional compu- tation approach of transferring data to CPU is no longer suitable especially with the cost it imposes. Given the increasing storage capacities, moving extensive data volumes between storage and compute cannot scale. Hence high-performance data processing mechanisms are needed which may be demonstrated in bringing compute closer to data. Generating insight where data is stored helps deal with energy efficiency, low latency as well as security. Storage bus bandwidth is also saved when only computation results are delivered to the host memory. Various applications including database acceleration, machine learning, artificial intelligence, off-loading (compression/encryption/encoding) and others can perform better and become more scalable if the “move process to data” paradigm is applied. Embedding processing engines inside the Solid-State Drives (SSDs) transforming them to Computational Storage Devices (CSDs) or inside memories usually Random Access Memories (RAMs) provides the needed data processing solution.
We review the prior art on near-data processing with a focus on in-storage processing and in-memory computing. We examine the applications supported by the different ar- chitectures and explore the different metrics for evaluating Near Data Processing (NDP) applications. We also discuss how different architectures can benefit from one another in addition to identifying the main challenges and potential gaps for future research directions.
In our work, we explore application of Processing-In-Memory (PIM) to address data integrity through the inclusion of Cyclic Redundancy Check (CRC) compute units as well as cryptographic mechanisms, specifically Advanced Encryption Standard (AES), within the Dynamic RAM (DRAM) controller, High Bandwidth Memory 3 (HBM3). JEDEC specification for HBM3 is studied carefully and verified before the addition of PIM units to determine the required design parameters for each block. The whole architecture is designed using verilog HDL and finally compiled in Siemens’ prototyping flow to measure the area and power difference incurred by adding PIM units.
We conclude by summarizing the fundamentals required for pushing NDP and discuss the future research directions that are needed to maximize the benefits.