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العنوان
Design of Programmable Multi-Standard RF-to-Digital Receiver for Wideband Wireless Applications /
المؤلف
Sakr, Ahmed Elsayed Muhammad.
هيئة الاعداد
باحث / أحمد السيد محمد صقر
مشرف / عزيزة إبراهيم حسين
مشرف / غزال عبد العاطي فهمي
مشرف / محمود أحمد عبدالغني
الموضوع
Electronic circuits. Electronics. Microelectronics.
تاريخ النشر
2022.
عدد الصفحات
54 p. :
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/2022
مكان الإجازة
جامعة المنيا - كلية الهندسه - الهندسة الكهربية
الفهرس
Only 14 pages are availabe for public view

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from 69

Abstract

Modern wireless networks are allocated in different frequency bands and have different specifications. However, many wireless devices are required to support different standards which is the case for mobile devices and IoT. For example, a modern mobile device usually supports 5G or 4G besides older generations back to 2G, WiFi standards 802.11 a/b/g/n/ac and Bluetooth with its different versions. To support all these standards, an increasing complexity is added to the design of RF front-end which should be more flexible and more programmable.
Software-defined-radio SDR aims to achieve a flexible front-end that is fully programmable and flexible in order to support more standards in different frequency bands and with different specifications. It takes advantage of the increasing enhancements in IC fabrication processes which enables performing signal processing in digital domain with high speed and accuracy more than what analog signal processing can achieve.
In this work, a review of traditional receivers as well as multistandard receivers and SDRs are performed, then an SDR based on Pulse-width-modulation PWM RF-to-digital receiver is demonstrated. The chosen PWM based SDR is simulated using MATLAB Simulink model to verify its performance.
PWM based Receivers’ performance depends on the performance of the high speed comparator. Different types of high speed comparators are reviewed. A high speed comparator with clock frequency up to 10GHz is designed and simulated using Cadence Virtuoso. The design can achieve a resolution of 13.28 bits. At a clock of 1GHz and 10.11 bits at a clock up to 10GHz with a common mode range from 0V to 600 mV. It was designed using TSMC 65nm technology.