الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
Designing low power circuits is a major target meanwhile. Governments and different initiatives encourage designing low power circuits to reduce power consumption worldwide. Customers are interested in low power designs due to different reasons as longer battery life. SoC can be implemented using dynamic and/or static CMOS logics. A dynamic CMOS logic uses two phases to evaluate a designed logic, which are: preparation phase and evaluation phases. The preparation phase is named pre-charge phase and pre-discharge phase for n-type and p-type dynamic logics, respectively. Dynamic power consumption of a dynamic logic increases when successive preparation and evaluation phases result in different voltage levels at its output node.
This research proposes new methods to reduce a circuit’s power consumption by controlling the preparation and the evaluation phases of dynamic logics. New methods are proposed to design single stage and pipelined systems to produce circuits, which consume less power than circuits implemented using the traditional techniques. Different techniques are proposed to define which dynamic logics are recommended to be modified to reduce a circuit’s power consumption. Modifying dynamic logics is also used to conditionally improving a circuit’s speed. New methods, flip-flops, and latches are proposed to use new proposed preparation and evaluation controlled dynamic logics effectively by single and multi-stage systems. New approach and netlist diagram are proposed to highlight high power consumption parts of a design and illustrate it in a simple way to ease its analysis and improve its power consumption. Finally, a new flow is proposed to modify an implemented circuit to produce a better version, which consumes less power and operates at a higher speed.
Experimental results show the efficiency of the proposed techniques to reduce a circuit’s power consumption and conditionally improving its speed. It also shows the ability of using the new techniques with currently used ones versus different and variant current and future operating conditions. The new proposed techniques are compared versus a new recently proposed power reduction technique. Comparison results using tiny, intermediate side, and large size designs show that the new proposed techniques give better results for power consumption, area, and speed aspects. The new proposed techniques show up to 59% power reduction compared to the traditional techniques with improving a circuit’s performance by 3× of its original maximum operating frequency at the cost of an extra 12.3% increase in area.