الفهرس 
Motivation
Proposed PI-based CDR CircuitOnly 14 pages are availabe for public view
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Abstract
This thesis presents system and circuit design techniques for fast-locking all- digital phase-interpolator (PI)-based clock and data recovery (CDR) circuits. The target application is burst-mode (BM) communication systems such as passive optical networks (PONs), memory interfaces and energy proportional serial-links with multi-channel operation in deep sub-micron CMOS technologies.
The objective of this thesis is driven by the need for fast-locking CDR ar- chitectures that can be used for BM transmission without sacrificing the jitter performance — a trade-off commonly encountered in the design of BM-CDR cir- cuits. The proposed technique allows closed-loop PI-based CDR circuits to meet the ultra-short locking time requirements set by BM communication systems. The main advantage of the proposed technique is maintaining superior jitter perfor- mance by the feedback action in contrast to common open-loop architectures.
On the system level, a new phase search technique that improves the locking speed of conventional (PI)-based CDR circuits is proposed. This technique em- ploys successive approximation register (SAR) algorithm that achieves fast phase locking through binary phase search, instead of following the typical phase track- ing trajectories of closed-loop feedback systems. The SAR algorithm is activated at startup or at the beginning of new data bursts to achieve phase lock in few tens of bit-periods. Once lock is achieved, the SAR algorithm is deactivated and the result is passed to a digital loop filter (DLF) of a conventional PI-based CDR to carry out further phase tracking and maintain the required jitter performance.
On the circuit level, the relatively short delay of the CDR loop encompassing the SAR algorithm (SAR-CDR) is exploited to achieve further improvements in the locking speed by operating its constituent blocks at a higher system frequency. This frequency is independent of the main clock supplied to the rest of the system and is set to its maximum value according to the loop delay. This results in additional boost to the locking speed and allows PI-based CDRs to achieve phase lock in a tiny fraction of the time achieved by conventional designs. To reduce the total area, block reuse is employed by placing the SAR block in place of the most significant N -bits of the Accumulator (ACC) feedback register. This is achieved by modifying the conventional design of the SAR unit.
To demonstrate the effectiveness of the proposed phase locking technique, a 10 Gbps half-rate all-digital PI-based CDR circuit that targets the stringent SONET OC-192 jitter specifications is analyzed and designed. A top-down design methodology is adopted throughout this work for implementing the proposed CDR circuit in a standard 65 nm low-power CMOS technology with 1.2 V supply. The design process begins by developing a linearized frequency-domain model to opti- mize the system parameters and extract the different blocks requirements for the targeted system specifications. Moreover, system functionality and performance are verified using time-domain behavioral models built with MATLAB/Simulink and Verilog-A. Next, each block is designed, simulated and its performance is veri- fied across process and temperature corners with post-layout simulations. Finally, the complete system is integrated and the performance improvements are verified and compared to the performance of state-of-the-art open-loop CDR architectures.
The implemented CDR employing the proposed technique shows 62.5–125-fold locking speed improvement by reducing the locking time from 800 ns to only
6.4 –12.5 ns with ±60 ppm maximum tolerable frequency offset between the trans-
mitter and the receiver. It consumes 8.2 mW from 1.2 V supply with an energy per bit FoM of less than 1 pJ/Bit while occupying an active area of 70µm × 90µm.