الفهرس 
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Abstract
Nowadays, multimedia data are closely related to many aspects of daily
life, including education, commerce, and politics. As the multimedia data itself
is not protected, and may be stolen during the transmission process. Thus, to
maintain security, multimedia data should be protected before transmission or
redistribution. Typical protection method is by using encryption techniques [1].
Reprogrammable hardware devices are highly attractive options for the
implementation of encryption algorithms. During the selection process of the
selected encryption techniques, an important criterion was the efficiency of the
cipher in different platforms, including FPGAs. Since 2001, various
implementations have consequently been proposed, exploring the different
possible design tradeoffs ranging from the highest throughput to the smallest
area [2]. Each of those implementations usually focuses on a particular
understanding of “efficiency”. Furthermore, every time a new hardware
platform is introduced, a new implementation is to be made in order to comply
with and take advantage of its specificities [3].
This thesis presents a reconfigurable hardware implementation of the
DES, 3DES, IDEA, AES and RC4 algorithms. This is achieved by combining
pipelining concept of these methods. The selected designs are implemented on
Xilinx Spartan-3A FPGA technology.
Implementing cryptographic algorithms on reconfigurable hardware
provides major benefits over VLSI and software platforms since they offer high
speed similar to VLSI and high flexibility similar to software. VLSI
implementations are fast but must be designed all the way from behavioral.